Design and Performance Analysis of Logic Circ...

Design and Performance Analysis of Logic Circuits using FinFet Technology

Author Name : Aaqib Rasool, Rajeshwar Singh

ABSTRACT

As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases, the short channel effect(SCE) becomes a dominating concern in VLSI. The Short channel effect causes an exponential increase in the leakage current. In order to reduce the SCE and hence leakage current, a new technology has been developed in recent years. In this recent technology a 3D multiple gate MOSFETs like FinFet (Fin Field Effect Transistor) has been developed which possess numerous advantages over conventional MOSFETs and has attracted many engineers and designers. FinFet is the new growing technology that works in the nm range to minimize short channel effects. Many companies (like Intel) have started using FinFet technology.

This document is a review paper of current researches on FinFet technology and discusses how it can be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.) and memory devices. Various parameters of FinFet like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software (HSpice) were used to simulate power, delay, power delay product, average power dissipation and energy delay product. Thus, FinFet technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range.

Keywords: FinFet, MOSFET, GDI, Short channel effects, Power Consumption, power-delay product.