Designing Low Power Mac Unit Design Using Blo...

Designing Low Power Mac Unit Design Using Block Enabling Technique

Author Name : Dr B. Rama Rao, B. Naveen Kumar, S. Nikhil, D. Rohit, D. Durga Prasad, K. Vikranth

ABSTRACT

Real-time signal processing requires a high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieving a high-performance digital signal processing system. This work aims to design a low-power MAC unit with a block enabling technique to save power. Firstly, a 1-bit MAC unit is designed, with appropriate geometries that give optimized power, area, and delay. The delay in the pipeline stages in the MAC unit is estimated based on which a control unit is designed to control the data flow between the MAC blocks for low power. Similarly, the N-bit MAC unit is designed and controlled for low power using a control logic that enables the pipelined stages at the appropriate time. The adder cell design has the advantage of high operational speed, small transistor count, and low power. If we want to implement the MAC unit, that can be possible using CMOS technology using the CADENCE VIRTUOSO tool with 0.18um size. This project also investigates various architectures of multipliers and adders which are suitable for the implementation of high throughput signal processing and at the same time to achieve low power consumption. The whole MAC chip is operated at 125 MHz using a 1.8 V power supply. The power is reduced by 65% using the block enabling technique compared to the normal design.

Keywords: Low Power, MAC, clock gating, block enable, multiplier.